Documentation of axi_interconnect release

This document contains technical documentation for the axi_interconnect FPGA module. It is generated from release axi_interconnect-0.0.0 at 2023-02-28 07:21.

Release notes

Changelogs from Truestream follow the keep a changelog format. Version numbers follow the semantic versioning scheme: MAJOR.MINOR.PATCH+HASH.

  • MAJOR will be incremented for incompatible API or functionality changes.

  • MINOR will be incremented when new functionality is added in a backwards compatible manner.

  • PATCH will be incremented for backwards compatible bug fixes.

The HASH field is the Git SHA that the release was made from. It is included in the version number for internal traceability.

Release history and changelog follows below.

1.0.0+2e2e9c00 - (24 march 2021)

Initial release.

Design details

See the Module axi_interconnect page for an overview and specification of the axi_interconnect module. Here you will also find a technical description of the different sub-modules.


This module has the following dependencies:

  • The open-source hdl_modules project version 2.0.0.

  • The Truestream module axi_data_width_converter version 2.1.0.

  • The Truestream module axi_crossbar version 3.1.0.

Library name

This module’s source files shall be compiled to a VHDL library symbolically named axi_interconnect.