Documentation of axi_data_width_converter release

This document contains technical documentation for the axi_data_width_converter FPGA module. It is generated from release axi_data_width_converter-0.0.0 at 2023-02-28 07:21.

Release notes

Changelogs from Truestream follow the keep a changelog format. Version numbers follow the semantic versioning scheme: MAJOR.MINOR.PATCH+HASH.

  • MAJOR will be incremented for incompatible API or functionality changes.

  • MINOR will be incremented when new functionality is added in a backwards compatible manner.

  • PATCH will be incremented for backwards compatible bug fixes.

The HASH field is the Git SHA that the release was made from. It is included in the version number for internal traceability.

Release history and changelog follows below.

2.1.0+345fa4e2 - (28 february 2023)


  • Support ID width of zero.

Bug fixes

  • Fix bug when downconverting read transactions, where a narrow burst might give the wrong RID.

2.0.0+6e780c13 - (21 august 2020)

Breaking changes

  • Adapt for tsfpga version 4.0.0

1.2.1+708d54f2 - (12 june 2020)


  • Adapt module to handle AxSIZE, with restrictions.

1.1.0+a65a9643 - (21 may 2020)


  • Add id_width generic. Saves resources by only using the necessary bits of the ID word.

1.0.0+751bbb32 - (20 may 2020)

Initial release.

Design details

See the Module axi_data_width_converter page for an overview and specification of the axi_data_width_converter module. Here you will also find a technical description of the different sub-modules.


This module has the following dependencies:

Library name

This module’s source files shall be compiled to a VHDL library symbolically named axi_data_width_converter.