Documentation of axi_crossbar release
This document contains technical documentation for the
axi_crossbar FPGA module.
It is generated from release
axi_crossbar-0.0.0 at 2023-02-28 07:21.
Changelogs from Truestream follow the keep a changelog format.
Version numbers follow the semantic versioning scheme:
MAJORwill be incremented for incompatible API or functionality changes.
MINORwill be incremented when new functionality is added in a backwards compatible manner.
PATCHwill be incremented for backwards compatible bug fixes.
HASH field is the Git SHA that the release was made from.
It is included in the version number for internal traceability.
Release history and changelog follows below.
3.1.0+73746267 - (28 february 2023)
Add support for passthrough mode (
num_left_ports = 1) that consumes no resources (unless asynchronous operation is enabled).
3.0.0+a4f1024a - (24 march 2021)
Break out axi_write_crossbar_core with simpler interface. The existing axi_write_crossbar instantiates the new core with no functional changes.
Adapt for latest tsfpga.
2.0.0+c995aaf0 - (21 august 2020)
Adapt for tsfpga version 4.0.0
1.0.0+84f2ce18 - (25 june 2020)
See the Module axi_crossbar page for an overview and specification of the
Here you will also find a technical description of the different sub-modules.
This module has the following dependencies:
The open-source hdl_modules project version
This module’s source files shall be compiled to a VHDL library symbolically named