Our Products

On this page, we list the FPGA IPs that are currently available from Truestream. You may find free implementations online or in EDA tools in a few cases, but none of them can match our combination of qualities:

Very low resource utilization compared to competitors, due to intensive area optimization with automated size checkers.
Guaranteed error-free operation. We use automatic testbenches and automatic tests on devices to ensure proper operation. Should any errors creep in, we will fix them at no cost to you.
Extensive use of generics, which makes IPs very portable and customizable according to user parameters.
Proper and up-to-date documentation.
Intuitive and user-friendly interfaces.
Delivery format is human-readable source code. This is easier to use than an encrypted IP core and much faster to simulate and build.

Using IPs with these qualities will significantly improve your time to market. There is no need for you to waste time on development, and you will not waste time on hard-to-find bugs. In combination with the low resource utilization you will be able to get even more out of your FPGA design. To learn more, don’t hesitate to contact us at info@truestream.se. If you want any other IP to be designed with these qualities, contact us for a non-binding discussion.

We are also active in the open-source FPGA community. We use many open-source tools and even run several projects of our own. Truestream employees are encouraged to contribute in open-source projects on company time.

AXI4-TO-AXI3 CONVERTER

The AXI4-to-AXI3 converter is a VHDL IP developed by Truestream. It adapts AXI4 transactions to be compliant with the older version of the standard. It is designed to have a very small logic footprint while maintaining full throughput. See the documents below for more details.

AXI4-to-AXI3 converter product sheet (PDF)
AXI4-to-AXI3 converter documentation (HTML)

AXI CROSSBAR

The AXI crossbar is a VHDL IP developed by Truestream. It performs N-to-1 arbitration of AXI buses. It is designed to have a very small logic footprint while maintaining full throughput. See the documents below for more details.

AXI crossbar product sheet (PDF)
AXI crossbar documentation (HTML)

AXI DATA WIDTH CONVERTER

The AXI data width converter is a VHDL IP developed by Truestream. It can be used for upconversion and downconversion of AXI read/write transactions. The IP is designed to be very resource efficient but still achieve high performance. See the documents below for more details.

AXI data width converter product sheet (PDF)
AXI data width converter documentation (HTML)

AXI INTERCONNECT

The AXI interconnect is a VHDL IP developed by Truestream. It is used to connect many AXI masters, which may be of different widths and in different clock domains, to a single physical AXI port. It guarantees 100% throughput in all scenarios with no clock cycles wasted. See the documents below for more details.

AXI interconnect product sheet (PDF)
AXI interconnect documentation (HTML)

AXI MASTER

The AXI master, also known as a “data mover” or “AXI MM2S/S2MM”, is a VHDL IP developed by Truestream. It provides a simple memory read/write interface that hides the complexity of raw AXI transactions. This Truestream IP guarantees full bus utilization while having a very small logic footprint. See the documents below for more details.

AXI master product sheet (PDF)
AXI master documentation (HTML)

HDL_MODULES

The open-source project hdl_modules is authored and maintained by the Truestream team. It is a collection of reusable, high-quality, peer-reviewed VHDL building blocks. The modules are designed to be reusable and portable, while having a clean and intuitive interface.

Complete documentation is available on the website: https://hdl-modules.com

This project is not a commercial interest of ours and is run entirely as an open-source community project. There are no paid premiums and no strings attached. It is released under the permissive BSD 3-Clause License. You are welcome to clone, modify, and submit patches at the gitlab page: https://gitlab.com/hdl_modules/hdl_modules

HDL_REGISTERS

The open-source project hdl_registers, an HDL register generator fast enough to run in real time, is authored and maintained by the Truestream team. It reduces time and effort, and minimizes errors, compared to a manual handling of registers. It can easily be plugged into your development environment so that VHDL register code generation is done before each build and simulation. For your FPGA release artifacts it can generate headers and documentation.

Complete documentation is available on the website: https://hdl-registers.com

OFF-CHIP FIFO

The off-chip FIFO is a VHDL IP developed by Truestream. It implements a FIFO structure that stores data in DDR SDRAM, unlike traditional FIFOs that use Block RAM or LUTRAM. The IP has unique versatility and user configurability while maintaining a very small logic footprint. See the documents below for more details.

Off-chip FIFO product sheet (PDF)
Off-chip FIFO documentation (HTML)

SLOW FIR FILTER

The slow FIR filter is a VHDL IP developed by Truestream. It is designed for signal processing when the data sample rate is significantly lower than the clock frequency. It uses only a single DSP element and minimal LUT/FF compared to competitors. See the documents below for more details.

Slow FIR filter product sheet (PDF)
Slow FIR filter documentation (HTML)

TSFPGA

The open-source project tsfpga, a flexible and scalable development platform for modern FPGA projects, is authored and maintained by the Truestream team. With its Python-based build/simulation flow it is perfect for CI/CD and test-driven development. The API is simple and easy to use (a complete simulation project is set up in less than 15 lines).

Complete documentation is available on the website: https://tsfpga.com