This page lists the FPGA IPs that are currently available for purchase from Truestream. In some cases you would be able to find free implementations on the internet or in EDA tools, but none can match our combination of:

  • Very low resource utilization compared to competitors, thanks to heavy area optimization with automated size checkers.
  • Guaranteed bug free. We use automatic testbenches and automated on-device tests to ensure proper operation. If any errors are found we will correct them without charge.
  • Heavy use of generics, making IPs very portable and user-parameterizable.
  • Proper documentation that is up-to-date.
  • Intuitive and easy-to-use interfaces.
  • Delivery format is human-readable source code. This is easier to use compared to an encrypted IP core, and way faster to simulate and build.

Using IPs with these qualities will greatly improve your time to market. You will not have to spend any development time, and you will not waste any time on hard-to-find bugs. In combination with the low resource utilization you will be able to get even more out of your FPGA design. Feel free to contact us at info@truestream.se for more information. If you want any other IP developed with these qualities, please contact us and we will be happy to discuss that with you.

We are also active in the open source FPGA community. We make use of many open source tools, and even run a few projects of our own. Truestream employees are encouraged to contribute to open source projects on company time.

AXI4-TO-AXI3 CONVERTER

The AXI4-to-AXI3 converter is a VHDL IP developed by Truestream. It adapts AXI4 transactions to be compliant with the older version of the standard. It is designed to have a very small logic footprint while maintaining full throughput. See the documents below for more details.

AXI4-to-AXI3 converter product sheet (PDF)
AXI4-to-AXI3 converter documentation (HTML)

AXI CROSSBAR

The AXI crossbar is a VHDL IP developed by Truestream. It performs N-to-1 arbitration of AXI buses. It is designed to have a very small logic footprint while maintaining full throughput. See the documents below for more details.

AXI crossbar product sheet (PDF)
AXI crossbar documentation (HTML)

AXI DATA WIDTH CONVERTER

The AXI data width converter is a VHDL IP developed by Truestream. It can be used for upconversion and downconversion of AXI read/write transactions. The IP is designed to be very resource efficient but still achieve high performance. See the documents below for more details.

AXI data width converter product sheet (PDF)
AXI data width converter documentation (HTML)

AXI INTERCONNECT

The AXI interconnect is a VHDL IP developed by Truestream. It is used to connect many AXI masters, that might be of different widths and in different clock domains, to a single physical AXI port. It guarantees 100% throughput in all scenarios with no clock cycles wasted. See the documents below for more details.

AXI interconnect product sheet (PDF)
AXI interconnect documentation (HTML)

AXI MASTER

The AXI master, also known as a “data mover” or “AXI MM2S/S2MM”, is a VHDL IP developed by Truestream. It provides a simple memory read/write interface that hides the complexity of raw AXI transactions. This IP by Truestream guarantees full bus utilization and yet has a very small logic footprint. See the documents below for more details.

AXI master product sheet (PDF)
AXI master documentation (HTML)

HDL_MODULES

The open source project hdl_modules is authored and maintained by Truestream employees. It is a collection of reusable, high-quality, peer-reviewed VHDL building blocks. The modules are designed to be reusable and portable, while having a clean and intuitive interface.

This project is not a commercial interest of ours and is run completely as an open source community project. There are no paid premiums and no strings attached. It is released under the permissive BSD 3-Clause License. You are welcome to clone, modify, and submit patches at the gitlab page: https://gitlab.com/hdl_modules/hdl_modules

Complete documentation is available on the website: https://hdl-modules.com

HDL_REGISTERS

The open source project hdl_registers, a HDL register generator fast enough to be run in real time, is authored and maintained by Truestream employees. It reduces time and effort, and minimizes errors, compared to a manual handling of registers.

This project is not a commercial interest of ours and is run completely as an open source community project. There are no paid premiums and no strings attached. It is released under the permissive BSD 3-Clause License. You are welcome to clone, modify, and submit patches at the gitlab page: https://gitlab.com/hdl_registers/hdl_registers

Complete documentation is available on the website: https://hdl-registers.com

OFF-CHIP FIFO

The off-chip FIFO is a VHDL IP developed by Truestream. It implements a FIFO structure that stores data in DDR SDRAM, unlike traditional FIFOs that utilize Block RAM or LUTRAM. The IP is uniquely versatile and user-configurable, while maintaining a very small logic footprint. See the documents below for more details.

Off-chip FIFO product sheet (PDF)
Off-chip FIFO documentation (HTML)

SLOW FIR FILTER

The slow FIR filter is a VHDL IP developed by Truestream. It is designed for signal processing when the data sample rate is significantly lower than the clock frequency. It uses only a single DSP element and minimal LUT/FF compared to competitors. See the documents below for more details.

Slow FIR filter product sheet (PDF)
Slow FIR filter documentation (HTML)

TSFPGA

The open source project tsfpga, a project platform form modern FPGA development, is authored and maintained by Truestream employees. With its python build/simulation flow it is perfect for CI/CD and test-driven development. Focus has been placed on flexibility and modularization, achieving scalability even in very large multi-vendor code bases.

This project is not a commercial interest of ours and is run completely as an open source community project. There are no paid premiums and no strings attached. It is released under the permissive BSD 3-Clause License. You are welcome to clone, modify, and submit patches at the gitlab page: https://gitlab.com/tsfpga/tsfpga

Complete documentation is available on the website: https://tsfpga.com