Documentation of off_chip_fifo release
======================================

This document contains technical documentation for the ``off_chip_fifo`` FPGA module.
It is generated from release ``off_chip_fifo-0.0.0`` at 2023-02-28 07:21.


Release notes
-------------

Changelogs from Truestream follow the `keep a changelog <https://keepachangelog.com>`__ format.
Version numbers follow the `semantic versioning <https://semver.org>`__ scheme:
``MAJOR.MINOR.PATCH+HASH``.

* ``MAJOR`` will be incremented for incompatible API or functionality changes.
* ``MINOR`` will be incremented when new functionality is added in a backwards compatible manner.
* ``PATCH`` will be incremented for backwards compatible bug fixes.

The ``HASH`` field is the Git SHA that the release was made from.
It is included in the version number for internal traceability.

Release history and changelog follows below.

1.0.0+bbccb3f4 - (28 february 2023)
___________________________________

Initial release.



Design details
--------------

See the :ref:`module_off_chip_fifo` page for an overview and specification of the
``off_chip_fifo`` module.
Here you will also find a technical description of the different sub-modules.


Requirements
------------

This module has the following dependencies:

* The open-source `hdl_modules <https://hdl-modules.com>`__ project version ``2.0.0``.

* The Truestream module ``axi_master`` version ``1.0.0``.

* The Truestream module ``ring_buffer_manager`` version ``0.0.1``.




Library name
------------

This module's source files shall be compiled to a VHDL library symbolically named
``off_chip_fifo``.

.. toctree::
  :caption: Contents
  :hidden:

  modules/off_chip_fifo/off_chip_fifo.rst